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Verilog HDL : a guide to digital design synthesis.

By: Palnitkar, SamirMaterial type: TextTextPublication details: Sunsoft Press, 1996. ISBN: 0134516753Subject(s): Verilog (Computer hardware description language) | Digital electronics | Computers -- Circuits | Computer architectureDDC classification: 621.392
Partial contents:
1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- A. Strength Modeling and Advanced Net Definitions -- B. List of PLI Routines -- C. List of Keywords, System Tasks, and Compiler Directives -- D. Formal Syntax Definition -- E. Verilog Tidbits -- F. Verilog Examples.
Holdings
Item type Home library Call number Status Date due Barcode Item holds
Two Week Loan Two Week Loan College Lane Learning Resources Centre
Main Shelves 		621.392 PAL (Browse shelf(Opens below)) Available 4403661575
Total holds: 0

Enhanced descriptions from Syndetics:

Includes index.

1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- A. Strength Modeling and Advanced Net Definitions -- B. List of PLI Routines -- C. List of Keywords, System Tasks, and Compiler Directives -- D. Formal Syntax Definition -- E. Verilog Tidbits -- F. Verilog Examples.

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