Syndetics cover image
Image from Syndetics

VHDL made easy! / David Pellerin, Douglas Taylor.

By: Contributor(s): Material type: TextTextPublication details: Upper Saddle River, NJ : Prentice Hall, 1996.ISBN:
  • 0136507638
Subject(s): DDC classification:
  • 621.392 20
LOC classification:
  • TK7885.7
Contents:
1. Introduction -- 2. A First Look at VHDL -- 3. Exploring Objects and Data Types -- 4. Using Standard Logic -- 5. Understanding Concurrent Statements -- 6. Understanding Sequential Statements -- 7. Creating Modular Designs -- 8. Partitioning Your Design -- 9. Writing Test Benches -- Appendix A. Getting The Most Out of Synthesis -- Appendix B. A VITAL Primer -- Appendix C. Using VHDL Simulation -- Appendix D. Test Bench Generation from Timing Diagrams -- Appendix E. VHDL Keyword List -- Appendix F. Driving Game Listings -- Appendix G. Synopsys Textio Package -- Appendix H. Glossary -- Appendix I. Other Resources.
Holdings
Item type Home library Call number Status Date due Barcode Item holds
Two Week Loan Two Week Loan College Lane Learning Resources Centre Main Shelves 621.392 PEL (Browse shelf(Opens below)) Available 4404114470
Total holds: 0

Enhanced descriptions from Syndetics:

Includes index.

1. Introduction -- 2. A First Look at VHDL -- 3. Exploring Objects and Data Types -- 4. Using Standard Logic -- 5. Understanding Concurrent Statements -- 6. Understanding Sequential Statements -- 7. Creating Modular Designs -- 8. Partitioning Your Design -- 9. Writing Test Benches -- Appendix A. Getting The Most Out of Synthesis -- Appendix B. A VITAL Primer -- Appendix C. Using VHDL Simulation -- Appendix D. Test Bench Generation from Timing Diagrams -- Appendix E. VHDL Keyword List -- Appendix F. Driving Game Listings -- Appendix G. Synopsys Textio Package -- Appendix H. Glossary -- Appendix I. Other Resources.